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_c4880 _d4880 |
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| 001 | 15889404 | ||
| 003 | BD-GzIUT | ||
| 005 | 20220825155210.0 | ||
| 008 | 090901s2010 njua b 001 0 eng | ||
| 010 | _a 2009034771 | ||
| 020 | _a9788131755020 | ||
| 020 | _a0137045794 (hardback : alk. paper) | ||
| 040 |
_aDLC _cDLC _dDLC |
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| 050 | 0 | 0 |
_aTK7885.7 _b.Z86 2010 |
| 082 | 0 | 0 |
_a621.39028553 _222 |
| 100 | 1 | _aZwoliński, Mark. | |
| 245 | 1 | 0 |
_aDigital system design with SystemVerilog / _cMark Zwolinski. |
| 260 |
_aNew Delhi : _bPearson, _cc2005. |
||
| 300 |
_axxix, 367 p. : _bill. ; _c24 cm. |
||
| 504 | _aIncludes bibliographical references and index. | ||
| 650 | 0 | _aVerilog (Computer hardware description language) | |
| 650 | 0 |
_aElectronic digital computers _xDesign and construction. |
|
| 650 | 0 | _aComputer simulation. | |
| 906 |
_a7 _bcbc _corignew _d1 _eecip _f20 _gy-gencatlg |
||
| 942 |
_2ddc _cBK |
||